There is a continuing desire to produce integrated MOS transistor logic circuits to implement functions that are increasingly sophisticated, complex and diverse. Consequently, there has been and continues to exist substantial development efforts aimed at improving the speed, packing density and functional capabilities of MOS logic devices. As a result, many different designs for high-speed, close packed MOS logic transistors have been developed. Characteristically, such logic transistors operate at voltage levels of five volts or less. Integrated circuits utilizing hundreds to hundreds of thousands of such transistors can now be fabricated on a single substrate die and, depending on the particular circuit design, can perform a great variety of logic functions.
Naturally, every integrated circuit must possess a suitable interface to interconnect with external devices. Where the interface must only support connections to other logic circuits, the required circuit interface function is typically implemented using logic voltage level drive subcircuits to propagate signals across the interface.
Interfacing logic circuits to devices that do not conveniently operate at logic voltage levels presents a special problem. Separate, specialized integrated circuits are conventionally employed to buffer the logic integrated circuits from external devices that, for example, require high-voltage levels to control the display of information, such as CRTs, plasma and fluorescent displays, or to control electromechanical devices, such as servos, relays and motors. These buffer integrated circuits generally implement a dual interface to provide voltage translation between logic interface levels and the levels required by the high-voltage external device. The required use of such buffer integrated circuits, as a practical matter, imposes a penalty of increased physical complexity, cost, size and power requirements in the resulting system. Integration of the high-voltage buffer function onto a primarily logic function integrated circuit is therefore desirable to minimize this penalty. Alternately, integration of a substantial logic function onto the buffer integrated circuit is desirable to increase the flexibility and functionally of the buffer circuit toward or to the level of a dedicated peripheral controller. Consequently, there is a need to provide high operational voltage MOS transistors on the same substrate as high-speed, comparatively low voltage MOS logic transistors.
A major impediment to providing high-voltage MOS transistors on a common substrate with high-speed MOS logic transistors is the complexity of the required fabrication process. The process must provide for the simultaneous fabrication of transistors optimized for high-voltage and others closely spaced, if not adjacent, for high-speed. Although both high and high-voltage transistors may require optimization with respect to the same physical phenomena, the specifics of the process optimization are typically quite different. For example, high-voltage transistor optimization requires maximizing the punch-through limit and reverse breakdown voltages of the transistor typically in preference over switching speed. The punch-through voltage limit is the drain to source voltage potential where the source and drain depletion regions first overlap. An overlap would establish an unconstrained conduction path between drain and source with a corresponding likely catastrophic failure of the device. Similarly, the reverse breakdown voltage limit is the reverse voltage potential at the drain/substrate junction that induces avalanche breakdown. Again, the result will be likely catastrophic failure of the device.
The primary emphasis for high-speed optimization is, in contrast, to shorten the transistor channel length, reduce the effective channel resistance and mitigate specific short channel effects such as gate threshold drift. High-speed transistors need be tailored only for punch-through and reverse breakdown voltages slightly in excess of the maximum logic voltage supply level. Channel resistance is minimized by maintaining the lowest possible channel doping level. Short channel gate voltage threshold drift is the result of the gate oxide of a short channel transistor being charged by hot electrons injected through the semiconductor/oxide interface barrier. Hot electrons are produced by the high electric field strength induced acceleration of electrons at the drain/channel junction. The high field strength is itself a product of the high-voltage gradient between the closely spaced source and drain regions (i.e. short channel).